Fundamentals of modern VLSI devices
Fundamentals of modern VLSI devices
Cache decay: exploiting generational behavior to reduce cache leakage power
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
DRG-cache: a data retention gated-ground cache for low power
Proceedings of the 39th annual Design Automation Conference
Dynamic Vt SRAM: a leakage tolerant cache memory for low voltage microprocessors
Proceedings of the 2002 international symposium on Low power electronics and design
Active leakage power optimization for FPGAs
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Larger-than-vdd forward body bias in sub-0.5V nanoscale CMOS
Proceedings of the 2004 international symposium on Low power electronics and design
Active mode leakage reduction using fine-grained forward body biasing strategy
Proceedings of the 2004 international symposium on Low power electronics and design
Power-Performance Trade-Offs in Nanometer-Scale Multi-Level Caches Considering Total Leakage
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Total leakage optimization strategies for multi-level caches
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Low-power programmable routing circuitry for FPGAs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Low-leakage robust SRAM cell design for sub-100nm technologies
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Impact of Body Bias on Delay Fault Testing of Sub-100 nm CMOS Circuits
Journal of Electronic Testing: Theory and Applications
Active mode leakage reduction using fine-grained forward body biasing strategy
Integration, the VLSI Journal
Optimal technology selection for minimizing energy and variability in low voltage applications
Proceedings of the 13th international symposium on Low power electronics and design
Case study of reliability-aware and low-power design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-power programmable FPGA routing circuitry
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Stacking SRAM banks for ultra low power standby mode operation
Proceedings of the 47th Design Automation Conference
A forward body-biased low-leakage SRAM cache: device, circuit and architecture considerations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Point and discard: a hard-error-tolerant architecture for non-volatile last level caches
Proceedings of the 49th Annual Design Automation Conference
OAP: an obstruction-aware cache management policy for STT-RAM last-level caches
Proceedings of the Conference on Design, Automation and Test in Europe
Endurance-aware cache line management for non-volatile caches
ACM Transactions on Architecture and Code Optimization (TACO)
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This paper presents a forward body-biasing (FBB) scheme for active leakage power reduction in cache memories. We utilize super high VT (threshold voltage) devices to suppress the leakage power in unselected portions of a cache while fast operation is achieve by dynamically forward body-biasing the selected SRAM cells. In order to generate a super high VT device, the 2-D halo doping profile was optimized considering different nanometer regime leakage mechanisms. The transition latency and energy overhead associated with FBB could be minimized by (i) waking up the SRAM cells ahead of the access and (ii) exploiting the cache access pattern. The combined device-circuit-architecture level techniques offer 64% total leakage reduction and 7.3% improvement in bitline delay compared to a previous state-of-the-art low-leakage SRAM technique.