Proceedings of the 2002 international symposium on Low power electronics and design
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
A forward body-biased low-leakage SRAM cache: device and architecture considerations
Proceedings of the 2003 international symposium on Low power electronics and design
Low-leakage asymmetric-cell SRAM
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Benefits and Costs of Power-Gating Technique
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
DRV-Fingerprinting: using data retention voltage of SRAM cells for chip identification
RFIDSec'12 Proceedings of the 8th international conference on Radio Frequency Identification: security and privacy issues
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On-chip SRAM caches have come to dominate the total chip area and leakage power consumed in state-of-the-art microprocessor designs. Such large memories are necessary to attain high performance, however it is critical to minimize the idle currents drawn while these SRAM banks are inactive. This work proposes a novel voltage reduction technique to reduce SRAM leakage power during the standby mode. The design employs an implicit voltage reduction method that "stacks" SRAM banks in series while these blocks are inactive. No explicit DC/DC converters are required to achieve the reduced voltages, which leads to large area reductions over techniques requiring on-chip regulation circuits. This stacking technique reduces the voltage on each block close to the absolute data retention voltage (DRV) of each cell, and achieves a maximum leakage power reduction of 93% from the active power mode. Simulation results show the stability of the scheme around corners, process variations, and on-chip noise.