Device optimization for ultra-low power digital sub-threshold operation
Proceedings of the 2004 international symposium on Low power electronics and design
High-performance CMOS variability in the 65-nm regime and beyond
IBM Journal of Research and Development - Advanced silicon technology
Predictive technology model for nano-CMOS design exploration
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Energy efficient near-threshold chip multi-processing
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Optimal technology selection for minimizing energy and variability in low voltage applications
Proceedings of the 13th international symposium on Low power electronics and design
The PARSEC benchmark suite: characterization and architectural implications
Proceedings of the 17th international conference on Parallel architectures and compilation techniques
Nanometer MOSFET effects on the minimum-energy point of 45nm subthreshold logic
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ACM SIGARCH Computer Architecture News
Misleading energy and performance claims in sub/near threshold digital systems
Proceedings of the International Conference on Computer-Aided Design
DSN '12 Proceedings of the 2012 42nd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN)
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Recent studies on near-threshold computing (NTC) investigated an optimum supply voltage which yields minimum energy per operation (Emin), and proposed various optimization techniques at the device, circuit, and architecture levels to further minimize Emin. However, most of these studies often overlooked the significance of (i) energy consumption of off-chip memory accesses; (ii) energy loss of voltage regulators (VRs); and (iii) the cost of chip area in NTC environment. In this paper, we first demonstrate the increasing significance of (i) and (ii) in NTC environment with a comprehensive set of device, circuit, and architectural-level models. Second, we explore technology optimization to improve the trade-off between platform energy and chip area considering (iii) in NTC environment. The experimental results show that our optimized technology achieves 4% to 21% energy reduction for various chip area constraints, achieving significant improvement in trade-off between platform energy and chip area for a wide range of parallel benchmarks.