Fundamentals of modern VLSI devices
Fundamentals of modern VLSI devices
Robust ultra-low power sub-threshold DTMOS logic
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Robust subthreshold logic for ultra-low power operation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Effects of global interconnect optimizations on performance estimation of deep submicron design
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
RT-Level Interconnect Optimization in DSM Regime
WVLSI '00 Proceedings of the IEEE Computer Society Annual Workshop on VLSI (WVLSI'00)
Dynamic VTH Scaling Scheme for Active Leakage Power Reduction
Proceedings of the conference on Design, automation and test in Europe
On the Optimization Power of Redundancy Addition and Removal for Sequential Logic Optimization
DSD '01 Proceedings of the Euromicro Symposium on Digital Systems Design
Logic Optimization of Unidirectional Circuits with Structural Methods
IOLTW '01 Proceedings of the Seventh International On-Line Testing Workshop
Proceedings of the conference on Design, automation and test in Europe: Proceedings
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Ultralow-voltage, minimum-energy CMOS
IBM Journal of Research and Development - Advanced silicon technology
Analyzing and modeling process balance for sub-threshold circuit design
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Numerical queue solution of thermal noise-induced soft errors in subthreshold CMOS devices
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Improving platform energy: chip area trade-off in near-threshold computing environment
Proceedings of the International Conference on Computer-Aided Design
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Digital circuits operated in the sub-threshold region (supply voltage less than the transistor threshold voltage) can have orders of magnitude power advantage over standard CMOS circuits for applications requiring ultra-low power and medium frequency of operation. It is possible to implement sub-threshold logic circuits using the standard transistors that are designed primarily for ultra high performance super-threshold logic design. However, a Si MOSFET so optimized for performance in the super-threshold regime is not the best device to use in the sub-threshold domain. In this paper, we propose device designs apt for sub-threshold operation. Results show that the optimized device improves the delay and power delay product (PDP) of an inverter chain by 44% and 51%, respectively, over the normal super-threshold device operated in the sub-threshold region.