Fundamentals of modern VLSI devices
Fundamentals of modern VLSI devices
Robust subthreshold logic for ultra-low power operation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Effects of global interconnect optimizations on performance estimation of deep submicron design
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
RT-Level Interconnect Optimization in DSM Regime
WVLSI '00 Proceedings of the IEEE Computer Society Annual Workshop on VLSI (WVLSI'00)
Dynamic VTH Scaling Scheme for Active Leakage Power Reduction
Proceedings of the conference on Design, automation and test in Europe
On the Optimization Power of Redundancy Addition and Removal for Sequential Logic Optimization
DSD '01 Proceedings of the Euromicro Symposium on Digital Systems Design
Logic Optimization of Unidirectional Circuits with Structural Methods
IOLTW '01 Proceedings of the Seventh International On-Line Testing Workshop
Device optimization for ultra-low power digital sub-threshold operation
Proceedings of the 2004 international symposium on Low power electronics and design
Ultra-low-power DLMS adaptive filter for hearing aid applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analysis of super cut-off transistors for ultralow power digital logic circuits
Proceedings of the 2006 international symposium on Low power electronics and design
An alternate design paradigm for low-power, low-cost, testable hybrid systems using scaled LTPS TFTs
ACM Journal on Emerging Technologies in Computing Systems (JETC)
A low-power parallel design of discrete wavelet transform using subthreshold voltage technology
CASES '08 Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems
Hybrid Super/Subthreshold Design of a Low Power Scalable-Throughput FFT Architecture
HiPEAC '09 Proceedings of the 4th International Conference on High Performance Embedded Architectures and Compilers
Interests and limitations of technology scaling for subthreshold logic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Energy-efficient subthreshold processor design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
From transistors to MEMS: throughput-aware power gating in CMOS circuits
Proceedings of the Conference on Design, Automation and Test in Europe
From Transistors to NEMS: Highly Efficient Power-Gating of CMOS Circuits
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Hybrid super/subthreshold design of a low power scalable-throughput FFT architecture
Transactions on High-Performance Embedded Architectures and Compilers IV
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This paper presents a novel design methodology for ultralow-power design using subthreshold leakage as the operating current (suitable for medium frequency of operation: tens to hundreds of millihertz). Standard design techniques suitable for super-threshold design can be used in the subthreshold region. However, in this study, it has been shown that a complete co-design at all levels of hierarchy (device, circuit, and architecture) is necessary to reduce the overall power consumption while achieving acceptable performance (hundreds of millihertz) in the subthreshold regime of operation. Simulation results of co-design on a five-tap finite-impulse-response filter shows ∼2.5 × improvement in throughput at iso-power compared to a conventional design.