Device optimization for ultra-low power digital sub-threshold operation
Proceedings of the 2004 international symposium on Low power electronics and design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
VLSI interconnect repeater for sub-threshold applications: a novel approach
ICNVS'10 Proceedings of the 12th international conference on Networking, VLSI and signal processing
Efficient interconnect design with novel repeater insertion for low power applications
WSEAS Transactions on Circuits and Systems
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Abstract: This paper attempts to determine the capabilities of existing Redundancy Addition and Removal (SRAR) techniques for logic optimization of sequential circuits. To this purpose, we compare this method with the Retiming and Resynthesis (RaR) techniques. For the RaR case the set of possible transformations has been established by relating them to STG transformations by other authors. Following these works, we first formally demonstrate that logic transformations provided by RaR are covered by SRAR as well. Then we also show that SRAR is able to identify transformations that cannot be found by RaR. This way we prove the higher potential of the Sequential Redundancy Addition and Removal over the Retiming and Resynthesis techniques.