Analysis of super cut-off transistors for ultralow power digital logic circuits

Authors:
Arijit Raychowdhury;Xuanyao Fong;Qikai Chen;Kaushik Roy
Affiliations:
Purdue University, IN;Purdue University, IN;Purdue University, IN;Purdue University, IN
Venue:
Proceedings of the 2006 international symposium on Low power electronics and design
Year:
2006

Citing 2
Cited 3

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Abstract

Super cut-off devices with sub-60mV/decade subthreshold swings have recently been demonstrated and being extensively studied. This paper presents a feasibility analysis of such tunneling devices for ultralow power subthreshold logic. Analysis shows that this device can deliver 800X higher performance (@iso-IOFF) compared to a MOSFET. The possible use of this device as a sleep transistor in conjunction with the regular Si MOSFET shows 2000X average improvement in leakage power compared to Si MOSFETs.