Logical effort: designing fast CMOS circuits
Logical effort: designing fast CMOS circuits
Theoretical and practical limits of dynamic voltage scaling
Proceedings of the 41st annual Design Automation Conference
Analysis of super cut-off transistors for ultralow power digital logic circuits
Proceedings of the 2006 international symposium on Low power electronics and design
Microelectronic Circuits Revised Edition
Microelectronic Circuits Revised Edition
A novel si-tunnel FET based SRAM design for ultra low-power 0.3V VDD applications
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
An energy-efficient heterogeneous CMP based on hybrid TFET-CMOS cores
Proceedings of the 48th Design Automation Conference
Variation-tolerant ultra low-power heterojunction tunnel FET SRAM design
NANOARCH '11 Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures
Energy efficient many-core processor for recognition and mining using spin-based memory
NANOARCH '11 Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures
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The theoretical lower limit of subthreshold swing in MOSFETs (60 mV/decade) significantly restricts low voltage operation since it results in a low ON to OFF current ratio at low supply voltages. This paper investigates extremely-low power circuits based on new Si/SiGe HEterojunction Tunneling Transistors (HETTs) that have subthreshold swing