RT-Level Interconnect Optimization in DSM Regime

Authors:
Srinivas Katkoori;Stelian Alupoaei
Affiliations:
-;-
Venue:
WVLSI '00 Proceedings of the IEEE Computer Society Annual Workshop on VLSI (WVLSI'00)
Year:
2000

Citing 0
Cited 4

Device optimization for ultra-low power digital sub-threshold operation

Proceedings of the 2004 international symposium on Low power electronics and design
Low-power design techniques for scaled technologies

Integration, the VLSI Journal - Special issue: Low-power design techniques
Computing with subthreshold leakage: device/circuit/architecture co-design for ultralow-power subthreshold operation

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-power design techniques for scaled technologies

Integration, the VLSI Journal - Special issue: Low-power design techniques

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Abstract

We propose global-net clustering based RT-level datapath design methodology. Static timing analysis identifies critical nets and critical primary input/output paths. Net clustering (based shared macro-cells and criticality) yields clusters wherein each cluster has interdependent nets. Clusters and nets within every cluster are prioritized based on number of critical nets, number of nets, and the total macro-cell area. We propose two approaches to generate layouts at RTL: constructive (cluster growth) approach and iterative improvement based (simulated annealing) approach. For datapaths implemented in 0.35-micron technology, for both approaches, we achieved an average decrease of 54% in longest wirelength and 53% in overall wirelength.