Clustered voltage scaling technique for low-power design
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Transistor sizing issues and tool for multi-threshold CMOS technology
DAC '97 Proceedings of the 34th annual Design Automation Conference
Energy minimization using multiple supply voltages
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Fundamentals of modern VLSI devices
Fundamentals of modern VLSI devices
Design and optimization of dual-threshold circuits for low-voltage low-power applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Gate-level design exploiting dual supply voltages for power-driven applications
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Synthesis of low power CMOS VLSI circuits using dual supply voltages
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Leakage control with efficient use of transistor stacks in single threshold CMOS
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A completey on-chip voltage regulation technique for low power digital circuits
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Challenges in clockgating for a low power ASIC methodology
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Run-time voltage hopping for low-power real-time systems
Proceedings of the 37th Annual Design Automation Conference
On gate level power optimization using dual-supply voltages
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 39th annual Design Automation Conference
Dynamic fine-grain leakage reduction using leakage-biased bitlines
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Drowsy caches: simple techniques for reducing leakage power
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Dynamic Vt SRAM: a leakage tolerant cache memory for low voltage microprocessors
Proceedings of the 2002 international symposium on Low power electronics and design
High performance and low power FIR filter design based on sharing multiplication
Proceedings of the 2002 international symposium on Low power electronics and design
Effects of global interconnect optimizations on performance estimation of deep submicron design
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
IDDQ Testing for Deep-Submicron ICs: Challenges and Solutions
IEEE Design & Test
Design Challenges of Technology Scaling
IEEE Micro
Beyond Moore's Law: The Interconnect Era
Computing in Science and Engineering
ICCD '96 Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors
Proceedings of the 40th annual Design Automation Conference
Reducing Power Consumption of Dedicated Processors Through Instruction Set Encoding
GLS '98 Proceedings of the Great Lakes Symposium on VLSI '98
Automatic Insertion of Gated Clocks at Register Transfer Level
VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
RT-Level Interconnect Optimization in DSM Regime
WVLSI '00 Proceedings of the IEEE Computer Society Annual Workshop on VLSI (WVLSI'00)
High-Performance Low-Power CMOS Circuits Using Multiple Channel Length and Multiple Oxide Thickness
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
A noise tolerant cache design to reduce gate and sub-threshold leakage in the nanometer regime
Proceedings of the 2003 international symposium on Low power electronics and design
Dynamic VTH Scaling Scheme for Active Leakage Power Reduction
Proceedings of the conference on Design, automation and test in Europe
VSV: L2-Miss-Driven Variable Supply-Voltage Scaling for Low Power
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Gate leakage reduction for scaled devices using transistor stacking
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Floorplan-Aware Low-Complexity Digital Filter Synthesis for Low-Power & High-Speed
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
DCG: deterministic clock-gating for low-power microprocessor design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2002 international symposium on low-power electronics and design (ISLPED)
Memory accesses reordering for interconnect power reduction in sum-of-products computations
IEEE Transactions on Signal Processing
Automatic synthesis of low-power gated-clock finite-state machines
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Gated clock routing for low-power microprocessor design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Variable wordlength soft-decision Viterbi decoder for power-efficient wireless LAN
Integration, the VLSI Journal
Ultra-low-power signaling challenges for subthreshold global interconnects
Integration, the VLSI Journal
Interconnect optimization to enhance the performance of subthreshold circuits
Microelectronics Journal
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Scaling of transistor feature sizes has provided a remarkable advancement in silicon industry for last three decades. However, while the performance increases due to scaling, the power density increases substantially every generation due to higher integration density. Furthermore, the demand for power-sensitive design has grown significantly in recent years due to tremendous growth in portable applications. Consequently, the need for power-efficient design techniques has grown considerably. Several efficient design techniques have been proposed to reduce both dynamic as well as static power in state-of-the-art VLSI circuit applications. In this paper, we discuss different circuit techniques that are used to maintain the power consumption (both static and dynamic) within a limit while achieving the highest possible performance.