High performance and low power FIR filter design based on sharing multiplication

Authors:
Jongsun Park;Woopyo Jeong;Hunsoo Choo;Hamid Mahmoodi-Meimand;Yongtao Wang;Kaushik Roy
Affiliations:
Purdue University, West Lafayette, IN;Purdue University, West Lafayette, IN;Purdue University, West Lafayette, IN;Purdue University, West Lafayette, IN;Purdue University, West Lafayette, IN;Purdue University, West Lafayette, IN
Venue:
Proceedings of the 2002 international symposium on Low power electronics and design
Year:
2002

Citing 4
Cited 3

Digital integrated circuits: a design perspective

Digital integrated circuits: a design perspective
Algorithmic and architectural techniques for low-power digital signal processing

Algorithmic and architectural techniques for low-power digital signal processing
Robust high-performance low-power carry select adder

ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Non-adaptive and adaptive filter implementation based on sharing multiplication

ICASSP '00 Proceedings of the Acoustics, Speech, and Signal Processing, 2000. on IEEE International Conference - Volume 01

Low-power design techniques for scaled technologies

Integration, the VLSI Journal - Special issue: Low-power design techniques
A Low Complexity and Low Power SoC Design Architecture for Adaptive MAI Suppression in CDMA Systems

Journal of VLSI Signal Processing Systems
Low-power design techniques for scaled technologies

Integration, the VLSI Journal - Special issue: Low-power design techniques

Quantified Score

Hi-index	0.01

Visualization

Abstract

We present a high performance and low power FIR filter design, which is based on computation sharing multiplier (CSHM). CSHM specifically targets computation re-use in vector-scalar products and is effectively used in our FIR filter design. Efficient circuit level techniques: a new carry select adder and conditional capture flip-flop (CCFF), are also used to further improve power and performance. The proposed FIR filter architecture was implemented in 0.25 &mgr;m technology. Experimental results on a 10 tap low pass CSHM FIR filter show speed and power improvement of 19% and 17%, respectively, with respect to an FIR filter based on Wallace tree multiplier.