High performance and low power FIR filter design based on sharing multiplication
Proceedings of the 2002 international symposium on Low power electronics and design
High-performance FIR filter design based on sharing multiplication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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FIR filtering can be expressed as multiplication of a vector by scalars. We present high-speed implementations for adaptive and nonadaptive filters based on a computation sharing multiplier which specifically targets computation re-use in vector-scalar products. The performance of the proposed implementation is compared with implementations based on carry save and Wallace tree multipliers in 0.6 /spl mu/ technology. We show that the sharing multiplier scheme improves speed by approximately 30% and 21% with respect to the Wallace tree multiplier based implementation for non-adaptive and adaptive filters, respectively.