Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Carry-Save Multiplication Schemes Without Final Addition
IEEE Transactions on Computers
Algorithmic and architectural techniques for low-power digital signal processing
Algorithmic and architectural techniques for low-power digital signal processing
Non-adaptive and adaptive filter implementation based on sharing multiplication
ICASSP '00 Proceedings of the Acoustics, Speech, and Signal Processing, 2000. on IEEE International Conference - Volume 01
Decision feedback equalizer with two's complement computation sharing multiplication
ICASSP '01 Proceedings of the Acoustics, Speech, and Signal Processing, 200. on IEEE International Conference - Volume 02
An efficient VLSI implementation for MC interpolation of AVS standard
PCM'04 Proceedings of the 5th Pacific Rim conference on Advances in Multimedia Information Processing - Volume Part III
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Finite impulse response (FIR) filtering can be expressed as multiplications of vectors by scalars. We present high-speed designs for FIR filters based on a computation sharing multiplier which specifically targets computation re-use in vector-scalar products. The performance of the proposed implementation is compared with implementations based on carry-save and Wallace tree multipliers in 0.35-µm technology. We show that sharing multiplier scheme improves speed by approximately 52 and 33% with respect to the FIR filter implementations based on the carry-save multiplier and Wallace tree multiplier, respectively. In addition, sharing multiplier scheme has a relatively small power delay product than other multiplier schemes. Using voltage scaling, power consumption of the FIR filter based on computation sharing multiplier can be reduced to 41% of the FIR filter based on the Wallace tree multiplier for the same frequency of operation.