A New Efficient VLSI Architecture for Full Search Block Matching Motion Estimation
VLSI-SOC '01 Proceedings of the IFIP TC10/WG10.5 Eleventh International Conference on Very Large Scale Integration of Systems-on/Chip: SOC Design Methodologies
Algorithms for Low Power FIR Filter Realization Using Differential Coefficients
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
High-performance FIR filter design based on sharing multiplication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An efficient VLSI architecture for motion compensation of AVS HDTV decoder
Journal of Computer Science and Technology - Special section on China AVS standard
Platform-independent MB-based AVS video standard implementation
Image Communication
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Advance Video Coding standard (AVS) [1] is the standard for compression and decompression in digital audio and video multimedia. The AVS Working Group was approved by the Science and Technology Department of Ministry of Information Industry of china on June 2002. AVS has employed a 4-tap interpolation FIR filter in its motion compensation (MC) part for high coding efficiency. But it is accompanied by increasing the complexity in calculation and memory access. And this problem makes MC one of the bottlenecks in the AVS system's VLSI implementation, especially for SDTV or HDTV which aggravate the problem heavily. Unfortunately, most FIR filter [3-5] have too low of input bandwidth to deal with it. In this paper, an efficient architecture for MC interpolation is described, and experimental results show that this architecture satisfies AVS decoder applications such as SDTV or HDTV.