Discrete-time signal processing
Discrete-time signal processing
Techniques for low power realization for FIR filters
ASP-DAC '95 Proceedings of the 1995 Asia and South Pacific Design Automation Conference
Low Power Digital CMOS Design
Survey of low power techniques for ROMs
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Low complexity FIR filters using factorization of perturbed coefficients
Proceedings of the conference on Design, automation and test in Europe
A Graph Theoretic Approach for Design and Synthesis of Multiplierless FIR Filters
Proceedings of the 12th international symposium on System synthesis
Low-power MIMO signal processing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Power Reduction Technique in Coefficient Multiplications Through Multiplier Characterization
Journal of VLSI Signal Processing Systems
An efficient VLSI implementation for MC interpolation of AVS standard
PCM'04 Proceedings of the 5th Pacific Rim conference on Advances in Multimedia Information Processing - Volume Part III
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We present a set of new algorithms for low-power realization of FIR filters which use various orders of differences between coefficients for computing the convolution with the input data. Also the results of computations are stored and reused, thus requiring more storage and storage accesses. These techniques result in a reduction in the computations necessary per convolution as compared to directly using the coefficients. It is shown analytically that this computational reduction at the price of more storage can result in a reduction in net energy dissipated. Realization of some example FIR filters using these algorithms is analyzed.