Introduction to algorithms
Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Combinatorial optimization
Low-Area/Power Parallel FIR Digital Filter Implementations
Journal of VLSI Signal Processing Systems
Algorithms for Low Power FIR Filter Realization Using Differential Coefficients
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Layout-driven architecture synthesis for high-speed digital filters
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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We present a novel approach which can be used to obtain multiplierless implementations of finite impulse response (FIR) digital filters. The main idea is to reorder filter coefficients such that an implementation based on differential coefficients requires only a few adders. We represent this problem using a graph in which vertices represent the coefficients and edges represent the resources required when the differential coefficient corresponding to the edge is used in a computation.We also present a graph model for an implementation based on second-order coefficient differences. The optimal solution to the coefficient reordering problem is the well known problem of finding the Hamiltonian path of smallest weight in this graph.We use two approaches to find the smallest weight Hamiltonian cycle; a greedy approach, and, the heuristic algorithm proposed by Lin and Kernighan. The power and potential of this approach is demonstrated by presenting results for large filters (lengths up to 300) which show that, in general, for 16-bit coefficients, the total number of adders required per coefficient is less than 2. Hence, high performance and/or low power filters can be designed and synthesized using the proposed approach.