Low-Area/Power Parallel FIR Digital Filter Implementations

Authors:
David A. Parker;Keshab K. Parhi
Affiliations:
Theseus Logic, Inc., 1080 Montreal Ave., Suite 200, St. Paul, MN 55116;Department of Electrical Engineering, University of Minnesota, Minneapolis, MN 55455
Venue:
Journal of VLSI Signal Processing Systems
Year:
1997

Citing 6
Cited 7

Fast FIR filtering: algorithms and implementations

Signal Processing
Multirate systems and filter banks

Multirate systems and filter banks
Efficient substitution of multiple constant multiplications by shifts and additions using iterative pairwise matching

DAC '94 Proceedings of the 31st annual Design Automation Conference
Power optimization in programmable processors and ASIC implementations of linear systems: transformation-based approach

DAC '96 Proceedings of the 33rd annual Design Automation Conference
Digit-Serial Computation

Digit-Serial Computation
Area-Efficient Parallel FIR Digital Filter Implementations

ASAP '96 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors

Field Programmable Gate Array Based Radar Front-End Digital Signal Processing

FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Implementation Image Data Convolutions Operations in FPGA Reconfigurable Structures for Real-Time Vision Systems

ITCC '00 Proceedings of the The International Conference on Information Technology: Coding and Computing (ITCC'00)
A Graph Theoretic Approach for Design and Synthesis of Multiplierless FIR Filters

Proceedings of the 12th international symposium on System synthesis
Low-power MIMO signal processing

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Frequency spectrum based low-area low-power parallel FIR filter design

EURASIP Journal on Applied Signal Processing
Low-area ASIC implementation for configurable coefficients FIR pulse shape filters of digital TV systems

Proceedings of the 21st annual symposium on Integrated circuits and system design
Design of low power multimode time-shared filters

ICICS'09 Proceedings of the 7th international conference on Information, communications and signal processing

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper presents a novel approach for implementing area-efficientparallel (block) finite impulse response (FIR) filters that require lesshardware than traditional block FIR filter implementations. Parallelprocessing is a powerful technique because it can be used to increase thethroughput of a FIR filter or reduce the power consumption of a FIR filter.However, a traditional block filter implementation causes a linear increasein the hardware cost (area) by a factor of L, the block size.In many design situations, this large hardware penalty cannot be tolerated.Therefore, it is important to design parallel FIR filter structures thatrequire less area than traditional block FIR filtering structures. In thispaper, we propose a method to design parallel FIR filter structures thatrequire a less-than-linear increase in the hardware cost. A novel adjacent coefficient sharing based sub-structure sharing techniqueis introduced and used to reduce the hardware cost of parallel FIR filters.A novel coefficient quantization technique, referred to as a scalable maximum absolute difference (MAD) quantizationprocess, is introduced and used to produce quantized filters withgood spectrum characteristics. By using a combination of fast FIR filteringalgorithms, a novel coefficient quantization process and area reductiontechniques, we show that parallel FIR filters can be implemented with up toa 45% reduction in hardware compared to traditional parallel FIRfilters.