Low-area ASIC implementation for configurable coefficients FIR pulse shape filters of digital TV systems

  • Authors:

  • Wagner Vieira Silvério;Janaína Domingues Costa;João Leonardo Fragoso;Julio Leão Silva, Jr.

  • Affiliations:

  • CEITEC - Centro de Excelência em Tecnologia Eletrônica Avançada, Porto Alegre, Brazil;CEITEC - Centro de Excelência em Tecnologia Eletrônica Avançada, Porto Alegre, Brazil;CEITEC - Centro de Excelência em Tecnologia Eletrônica Avançada, Porto Alegre, Brazil;CEITEC - Centro de Excelência em Tecnologia Eletrônica Avançada, Porto Alegre, Brazil

  • Venue:
  • Proceedings of the 21st annual symposium on Integrated circuits and system design
  • Year:
  • 2008

Quantified Score

Hi-index 0.00

Visualization

Abstract

Based on low area and low power techniques for FIR (Finite Impulse Response) filters, this paper proposes an area efficient implementation for configurable coefficients FIR pulse shape filters in the digital TV systems context. The structure proposed combines different FIR Filter hardware simplification techniques such as parallel and serial structures, polyphase decomposition, and symmetry of coefficients. By reducing the silicon area needed to implement digital circuits in ASIC (Aplication Specific integrated Circuit), the implementation cost is reduced. According to [6], the implementation cost of a digital circuit is linked with a function of the area in fourth power. Smaller circuits consume less energy and the respective parasite capacitance is decreased. Thus, digital designers aim at reducing area while complying with performance and functionally requirements.