DAC '94 Proceedings of the 31st annual Design Automation Conference
Low-Area/Power Parallel FIR Digital Filter Implementations
Journal of VLSI Signal Processing Systems
Synthesis of low power folded programmable coefficient FIR digital filters (short paper)
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Low power realization of FIR filters using multirate architectures
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Hi-index | 0.00 |
This paper proposes a new class of timeshared filtering architectures targeted at low power multimode portable wireless applications. The proposed structures exploit the increased cycle period available in fast filter algorithm based parallel processing structures to operate at a lower supply voltage, thereby reducing the power consumption. Further power reductions are obtained due to the reduced number of multiplications in fast filter algorithms. The paper also presents a novel power consumption model for various time-shared filter architectures in a voltage scaling regime. The proposed model can be used to investigate the impact of varying the throughput, filter architecture, filter lengths, and parallelism on the power consumption.