On-chip vs. off-chip memory: the data partitioning problem in embedded processor-based systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Embedded System Design: A Unified Hardware/Software Introduction
Embedded System Design: A Unified Hardware/Software Introduction
An efficient VLSI architecture for motion compensation of AVS HDTV decoder
Journal of Computer Science and Technology - Special section on China AVS standard
Efficient Implementation of Interpolation for AVS
CISP '08 Proceedings of the 2008 Congress on Image and Signal Processing, Vol. 3 - Volume 03
A motion vector predictor architecture for AVS and MPEG-2 HDTV decoder
PCM'06 Proceedings of the 7th Pacific Rim conference on Advances in Multimedia Information Processing
An efficient VLSI implementation for MC interpolation of AVS standard
PCM'04 Proceedings of the 5th Pacific Rim conference on Advances in Multimedia Information Processing - Volume Part III
An efficient VLSI architecture of VLD for AVS HDTV decoder
IEEE Transactions on Consumer Electronics
An AVS HDTV video decoder architecture employing efficient HW/SW partitioning
IEEE Transactions on Consumer Electronics
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AVS1-P2 is the newest video standard of Audio Video coding Standard (AVS) workgroup of China, which provides close performance to H.264/AVC main profile with lower complexity. In this paper, a platform-independent software package with macroblock-based (MB-based) architecture is proposed to facilitate AVS video standard implementation on embedded system. Compared with the frame-based architecture, which is commonly utilized for PC platform oriented video applications, the MB-based decoder performs all of the decoding processes, except the high-level syntax parsing, in a set of MB-based buffers with adequate size for saving the information of the current MB and the neighboring reference MBs to minimize the on-chip memory and to save the time consumed in on-chip/off-chip data transfer. By modifying the data flow and decoding hierarchy, simulating the data transfer between the on-chip memory and the off-chip memory, and modularizing the buffer definition and management for low-level decoding kernels, the MB-based system architecture provides over 80% reduction in on-chip memory compared to the frame-based architecture when decoding 720p sequences. The storage complexity is also analyzed by referencing the performance evaluation of the MB-based decoder. The MB-based decoder implementation provides an efficient reference to facilitate development of AVS applications on embedded system. The complexity analysis provides rough storage complexity requirements for AVS video standard implementation and optimization.