A motion vector predictor architecture for AVS and MPEG-2 HDTV decoder

  • Authors:

  • Junhao Zheng; Di Wu;Lei Deng;Don Xie;Wen Gao

  • Affiliations:

  • Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China;Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China;Department of Computer Science, Harbin Institute of Technology, Harbin, China;Grandview Semiconductor (BeiJing) Corporation;Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China

  • Venue:
  • PCM'06 Proceedings of the 7th Pacific Rim conference on Advances in Multimedia Information Processing
  • Year:
  • 2006

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Abstract

In the advanced Audio Video coding Standard (AVS), many efficient coding tools are adopted in motion compensation, such as new motion vector prediction, direct mode matching, variable block-sizes etc. However, these features enormously increase the computational complexity and the memory bandwidth requirement and make the traditional MV predictor more complicated. This paper proposes an efficient MV predictor architecture for both AVS and MPEG-2 decoder. The proposed architecture exploits the parallelism to accelerate the speed of operations and uses the dedicated design to optimize the memory access. In addition, it can reuse the on-chip buffer to support the MV error-resilience for MPEG-2 decoding. The design has been described in Verilog HDL and synthesized using 0.18μm CMOS cells library by Design Compiler. The circuit costs about 62k logic gates when the working frequency is set to 148.5MHz. This design can support the real-time MV predictor of HDTV 1080i video decoding for both AVS and MPEG-2.