High-performance FIR filter design based on sharing multiplication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
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We present an architecture of a high performance decision feedback equalizer based on a computation sharing multiplier. The computation sharing multiplier (CSHMR) uses a redundant number scheme and targets removal of computational redundancy by computation re-use. Use of CSHMR leads to high performance FIR filtering operation by re-using optimal precomputations. A decision feedback equalizer (DFE) implementation based on CSHMR in a 0.35 /spl mu/ technology shows 34% improvement in the operating speed over DFE using a Wallace tree multiplier.