Floorplan-Aware Low-Complexity Digital Filter Synthesis for Low-Power & High-Speed

Authors:
Dongku Kang;Hunsoo Choo;Kaushik Roy
Affiliations:
Purdue University, West Lafayette, IN;Purdue University, West Lafayette, IN;Purdue University, West Lafayette, IN
Venue:
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Year:
2004

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Low-power design techniques for scaled technologies

Integration, the VLSI Journal - Special issue: Low-power design techniques
Low-power design techniques for scaled technologies

Integration, the VLSI Journal - Special issue: Low-power design techniques

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Abstract

In this paper, we propose a floorplan-aware complexity reduction methodology for digital filters.The proposed scheme integrates high-level synthesis and floorplan to obtain improvement in both computational complexity and interconnect delay.Physical information of floorplan is incorporated into architecture synthesis.By considering interconnects while synthesizing reduced-complexity filters, the layout-centric architecture achieves better performance in the evolving scaled technologies.In our experiments, we achieved 15% improvement in critical-path delay over conventional design methodology.