New clock-gating techniques for low-power flip-flops
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Low-power design techniques for scaled technologies
Integration, the VLSI Journal - Special issue: Low-power design techniques
Low-power gated and buffered clock network construction
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Low-power design techniques for scaled technologies
Integration, the VLSI Journal - Special issue: Low-power design techniques
Unified gated flip-flops for reducing the clocking power in register circuits
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
Efficient automated clock gating using codel
SAMOS'06 Proceedings of the 6th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
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In synchronous circuits, the clock signal switches at every clock cycle and drives a large capacitance. As a result, the clock signal is a major source of dynamic power dissipation. Significant power savings can be obtained by identifying periods of inactivity in parts of the circuit, and disabling the clock to those parts of the circuit at the appropriate times. Selectively disabling the clock in this manner is referred to as clock gating. In this paper, we present a methodology to identify registers and flip flops in a circuit for which the clock input can be gated with a control sig nal. We also generate the combinational logic to produce this control signal. We present an algorithm to estimate the power saving obtained by gating the clock and the performance penalty (if any) associated with the introduction of gating logic. The algorithm also generates the clock gating logic which is inserted appropriately into the original circuit to produce a low power, gated clock version of the circuit.