New clock-gating techniques for low-power flip-flops

Authors:
A. G. M. Strollo;E. Napoli;D. De Caro
Affiliations:
University of Naples 'Federico II', Department of Electronic and Telecommunication Engineering, via Claudio, 21, Naples, Italy;University of Naples 'Federico II', Department of Electronic and Telecommunication Engineering, via Claudio, 21, Naples, Italy;University of Naples 'Federico II', Department of Electronic and Telecommunication Engineering, via Claudio, 21, Naples, Italy
Venue:
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Year:
2000

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Abstract

Two novel low power flip-flops are presented in the paper. Proposed flip-flops use new gating techniques that reduce power dissipation deactivating the clock signal. Presented circuits overcome the clock duty-cycle limitation of previously reported gated flip-flops.Circuit simulations with the inclusion of parasitics show that sensible power dissipation reduction is possible if input signal has reduced switching activity. A 16-bit counter is presented as a simple low power application.