ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
High-performance energy-efficient D-flip-flop circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
New clock-gating techniques for low-power flip-flops
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Automatic synthesis of low-power gated-clock finite-state machines
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Microprocessors, ASICs and DSPs form the core components of digital systems. Power aware computing on such systems necessitates both low power hardware design and software power optimization. Flip-flops are an integral component of digital circuits responsible for data storage. Hence, designing a low power flip-flop is of prime importance. In portable systems, considerable time is spent in idle or sleep mode. In this mode, leakage power is becoming a concern, hence reducing both active and leakage power is a necessity for overall power optimization. Hence, flip-flops which have the following features are desired: 1. Low active power during normal operation, 2. Low inherent leakage power during sleep mode and 3. Not only preventing spurious data to be passed through (data-gating) but also being capable of generating the desired output state for lower leakage power dissipation. Unlike static flops, with dynamic flops clock-gating is not directly possible, as such flops require the clock to be running continuously for proper functioning. This chapter describes a detailed comparison analysis of delay and power including leakage power Characteristics of existing flip-flops in literature. Further, the introduction of data-gating in dynamic flops to achieve high speed, low active power and at the same time, setting the output state to reduce leakage power in subsequent blocks is discussed. This shows good potential for active and leakage power optimization in digital CMOS circuits.