Analysis and design of low-energy flip-flops
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Optimization of scannable latches for low energy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
High-performance and low-power conditional discharge flip-flop
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-power clock branch sharing double-edge triggered flip-flop
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Activity-sensitive flip-flop and latch selection for reduced energy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A novel overlap-based logic cell: an efficient implementation of flip-flops with embedded logic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An experimental evaluation of real-time DVFS scheduling algorithms
Proceedings of the 5th Annual International Systems and Storage Conference
Static analysis of asynchronous clock domain crossings
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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This paper investigates performance, power, and energy efficiency of several CMOS master-slave D-flip-flops (DFF's). To improve performance and energy efficiency, a push-pull DFF and a push-pull isolation DFF are proposed. Among the five DFF's compared, the proposed push-pull isolation circuit is found to be the fastest with the best energy efficiency. Effects of using a double-pass-transistor logic (DPL) circuit and tri-state push-pull driver are also studied. Last, metastability characteristics of the five DFP's are also analyzed.