High-performance and low-power conditional discharge flip-flop

Authors:
Peiyi Zhao;Tarek K. Darwish;Magdy A. Bayoumi
Affiliations:
Center for Advanced Computer Studies, University of Louisiana at Lafayette, Lafayette, LA;Center for Advanced Computer Studies, University of Louisiana at Lafayette, Lafayette, LA;Center for Advanced Computer Studies, University of Louisiana at Lafayette, Lafayette, LA
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2004

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Abstract

In this paper, high-performance flip-flops are analyzed and classified into two categories: the conditional precharge and the conditional capture technologies. This classification is based on how to prevent or reduce the redundant internal switching activities. A new flip-flop is introduced: the conditional discharge flip-flop (CDFF). It is based on a new technology, known as the conditional discharge technology. This CDFF not only reduces the internal switching activities, but also generates less glitches at the output, while maintaining the negative setup time and small D-to-Q delay characteristics. With a data-switching activity of 37.5%, the proposed flip-flop can save up to 39% of the energy with the same speed as that for the fastest pulsed flip-flops.