Low-power clocked-pseudo-NMOS flip-flop for level conversion in dual supply systems

Authors:
Peiyi Zhao;Jason B. McNeely;Pradeep K. Golconda;Soujanya Venigalla;Nan Wang;Magdy A. Bayoumi;Weidong Kuang;Luke Downey
Affiliations:
Integrated Circuit Design and Embedded System Lab, Math and Computer Science Department, Chapman University, Orange, CA;Center for Advanced Computer Studies, University of Louisiana at Lafayette, Lafayette, LA;Intel Corporation, Folsom, CA;Intel Corporation, Folsom, CA;Department of Electrical and Computer Engineering, Institute of Technology,West Virginia University, Montgomery, VW;Center for Advanced Computer Studies, University of Louisiana at Lafayette, Lafayette, LA;Department of Electrical Engineering, Pan American University, Edinburg, TX;Integrated Circuit Design and Embedded System Lab, Math and Computer Science Department, Chapman University, Orange, CA
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2009

Citing 10
Cited 1

Digital integrated circuits: a design perspective

Digital integrated circuits: a design perspective
Comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flip-flops for high-performance microprocessors

ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Design of High-Performance Microprocessor Circuits

Design of High-Performance Microprocessor Circuits
Level conversion for dual-supply systems

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High-performance and low-power conditional discharge flip-flop

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High performance level conversion for dual VDD design

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Variation-tolerant circuits: circuit solutions and techniques

Proceedings of the 42nd annual Design Automation Conference
High Speed Soft-Error-Tolerant Latch and Flip-Flop Design for Multiple VDD Circuit

ISVLSI '07 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Low-power clock branch sharing double-edge triggered flip-flop

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analysis and Design of Digital Integrated Circuits

Analysis and Design of Digital Integrated Circuits

Design of sequential elements for low power clocking system

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

Clustered voltage scaling (CVS) is an effective way to decrease power dissipation. One of the design challenges is the design of an efficient level converter with fewer power and delay overheads. In this paper, level-shifting flip-flop topologies are investigated. Different level-shifting schemes are analyzed and classified into groups: differential style, n-type metal-oxide-semiconductor (NMOS) pass-transistor style, and precharged style. An efficient level-shifting scheme, the clocked-pseudo-NMOS (CPN) level conversion scheme, is presented. One novel level conversion flip-flop (CPN-LCFF) is proposed, which combines the conditional discharge technique and pseudo-NMOS technique. In view of power and delay, the new CPN-LCFF outperforms previous LCFF by over 8% and 15.6%, respectively.