A new family of sequential elements with built-in soft error tolerance for dual-VDD systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-power clocked-pseudo-NMOS flip-flop for level conversion in dual supply systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design of sequential elements for low power clocking system
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this paper, a novel soft-error-tolerant latch and a novel softerror- tolerant flip-flop are presented for multiple VDD circuit design. By utilizing local redundancy, the latch and the flip-flop can recover from soft errors caused by cosmic rays and particle strikes. By using output feedback, implicit pulsed clock, and conditional discharged techniques, the proposed flip-flop can behave as a level converter and without the problems of static leakage and redundant switching activity. Since the setup time of the new flip flop is negative, it can further mitigate the impact of single event transient (SET) at the D input of the flip-flop. Experimental results show that compared to the traditional D soft-error-tolerant latch, the delay of the new D latch is 29.1% less but with a more than 16.5% power reduction. Compared to the traditional high speed level converting flip-flop, the D-Q delay and power of the new flip-flop are about 47.7% and 54% less than those of the traditional one respectively.