Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic
DSN '02 Proceedings of the 2002 International Conference on Dependable Systems and Networks
Level conversion for dual-supply systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power minimization using simultaneous gate sizing, dual-Vdd and dual-Vth assignment
Proceedings of the 41st annual Design Automation Conference
Dependability Analysis of Nano-scale FinFET circuits
ISVLSI '06 Proceedings of the IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
High Speed Soft-Error-Tolerant Latch and Flip-Flop Design for Multiple VDD Circuit
ISVLSI '07 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Soft Error Rate Analysis for Combinational Logic Using An Accurate Electrical Masking Model
VLSID '07 Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems
Sequential element design with built-in soft error resilience
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analysis and Design of Digital Integrated Circuits
Analysis and Design of Digital Integrated Circuits
Gate sizing to radiation harden combinational logic
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
SEU tolerant robust latch design
VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
A layout-based approach for multiple event transient analysis
Proceedings of the 50th Annual Design Automation Conference
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In this paper, we propose some soft-error-tolerant latches and flip-flops that can be used in dual-VDD systems. By utilizing local redundancy and inner feedback techniques, the latches and flip-flops can recover from soft errors caused by cosmic rays and particle strikes. The proposed flip-flop can be used as a level shifter without the problems of static leakage and redundant switching activity. Implemented in a standard 0.18-µm technology, the proposed latches and flip-flops show superior performance compared to conventional ones in terms of delay and power while keeping the soft-error-tolerant characteristic. Experimental results show that compared to the traditional built-in soft-error-tolerant D latch, the D-QN delay of the new D latch is 29.1% less than that of the traditional built-in soft-error-tolerant D latch while consuming 16.5 % less power as well. The D-Q delay and power of the new flip-flop are about 47.7% and 54% less than those of the traditional high speed level-converting flip-flop, respectively. In addition, the proposed flip-flop is more robust to soft errors. The critical charge which represents the minimum charge at the D input required to cause an error of the flip-flop can be increased by more than 46.4 %. The time window during which the flip-flop will be erroneous caused by single-event upsets at the D input is reduced by more than 22.2%.