Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic
DSN '02 Proceedings of the 2002 International Conference on Dependable Systems and Networks
Multiple Transient Faults in Logic: An Issue for Next Generation ICs
DFT '05 Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
SEAT-LA: A Soft Error Analysis Tool for Combinational Logic
VLSID '06 Proceedings of the 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design
Multiple Event Transient Induced by Nuclear Reactions in CMOS Logic Cells
IOLTS '07 Proceedings of the 13th IEEE International On-Line Testing Symposium
Study of the effects of MBUs on the reliability of a 150 nm SRAM device
Proceedings of the 45th annual Design Automation Conference
A new family of sequential elements with built-in soft error tolerance for dual-VDD systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Sequential element design with built-in soft error resilience
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Statistical fault injection: quantified error and confidence
Proceedings of the Conference on Design, Automation and Test in Europe
Multiple transient faults in combinational and sequential circuits: a systematic approach
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
High-Performance Robust Latches
IEEE Transactions on Computers
Modeling and Optimization for Soft-Error Reliability of Sequential Circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
SCFIT: a FPGA-based fault injection technique for SEU fault model
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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With the emerging nanoscale CMOS technology, Multiple Event Transients (METs) originated from radiation strikes are expected to become more frequent than Single Event Transients (SETs). In this paper, a fast and accurate layout-based Soft Error Rate (SER) estimation technique with consideration of both SET and MET fault models is proposed. Unlike previous techniques in which the adjacent MET sites are obtained from logic-level netlist, we perform a comprehensive layout analysis to extract MET adjacent cells. It is shown that layout-based technique is the only effective solution for identification of adjacent cells as netlist-based techniques significantly underestimate the overall SER.