Mersenne twister: a 623-dimensionally equidistributed uniform pseudo-random number generator
ACM Transactions on Modeling and Computer Simulation (TOMACS) - Special issue on uniform random number generation
Fault Injection in VHDL Descriptions and Emulation
DFT '00 Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Exploiting FPGA-Based Techniques for Fault Injection Campaigns on VLSI Circuits
DFT '01 Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Comparison and Application of Different VHDL-Based Fault Injection Techniques
DFT '01 Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Self-Checking and Fault Tolerance Quality Assessment Using Fault Sampling
DFT '02 Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Bit Flip Injection in Processor-Based Architectures: A Case Study
IOLTW '02 Proceedings of the Proceedings of The Eighth IEEE International On-Line Testing Workshop (IOLTW'02)
New Techniques for Speeding-Up Fault-Injection Campaigns
Proceedings of the conference on Design, automation and test in Europe
Multi-Level Fault Injections in VHDL Descriptions: Alternative Approaches and Experiments
Journal of Electronic Testing: Theory and Applications
Detailed Comparison of Dependability Analyses Performed at RT and Gate Levels
DFT '03 Proceedings of the 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Area-Throughput Trade-Offs for Fully Pipelined 30 to 70 Gbits/s AES Processors
IEEE Transactions on Computers
A Flexible SoPC-based Fault Injection Environment
DDECS '06 Proceedings of the 2006 IEEE Design and Diagnostics of Electronic Circuits and systems
Double-Data-Rate Computation as a Countermeasure against Fault Analysis
IEEE Transactions on Computers
Feasibility analysis for robustness quantification by symbolic model checking
Formal Methods in System Design
Efficient soft error protection for commodity embedded microprocessors using profile information
Proceedings of the 13th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, Tools and Theory for Embedded Systems
Low cost control flow protection using abstract control signatures
Proceedings of the 14th ACM SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systems
CSER: HW/SW configurable soft-error resiliency for application specific instruction-set processors
Proceedings of the Conference on Design, Automation and Test in Europe
RASTER: runtime adaptive spatial/temporal error resiliency for embedded processors
Proceedings of the 50th Annual Design Automation Conference
A layout-based approach for multiple event transient analysis
Proceedings of the 50th Annual Design Automation Conference
DHASER: dynamic heterogeneous adaptation for soft-error resiliency in ASIP-based multi-core systems
Proceedings of the International Conference on Computer-Aided Design
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Fault injection has become a very classical method to determine the dependability of an integrated system with respect to soft errors. Due to the huge number of possible error configurations in complex circuits, a random selection of a subset of potential errors is usual in practical experiments. The main limitation of such a selection is the confidence in the outcomes that is never quantified in the articles. This paper proposes an approach to quantify both the error on the presented results and the confidence on the presented interval. The computation of the required number of faults to inject in order to achieve a given confidence and error interval is also discussed. Experimental results are shown and fully support the presented approach.