Fault Injection in VHDL Descriptions and Emulation

Authors:
Régis Leveugle
Affiliations:
-
Venue:
DFT '00 Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Year:
2000

Citing 0
Cited 10

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Early SEU Fault Injection in Digital, Analog and Mixed Signal Circuits: A Global Flow

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Soft error rate estimation and mitigation for SRAM-based FPGAs

Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
Combined Fault Classification and Error Propagation Analysis to Refine RT-Level Dependability Evaluation

Journal of Electronic Testing: Theory and Applications
Statistically translating low-level error probabilities to increase the accuracy and efficiency of reliability simulations in hardware description languages

Proceedings of the 18th ACM Great Lakes symposium on VLSI
Statistical fault injection: quantified error and confidence

Proceedings of the Conference on Design, Automation and Test in Europe
Radiation-induced Soft Errors: A Chip-level Modeling Perspective

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Abstract

Analyzing at an early stage of the design the potential faulty behaviors of a circuit becomes a major concern due to the increasing probability of faults. It is proposed to carry out such an analysis using fault injections in RT-level VHDL descriptions and hardware prototyping of the circuit under design. Injection of erroneous transitions is automated and results are presented.