Multi-Level Fault Injections in VHDL Descriptions: Alternative Approaches and Experiments
Journal of Electronic Testing: Theory and Applications
Early SEU Fault Injection in Digital, Analog and Mixed Signal Circuits: A Global Flow
Proceedings of the conference on Design, automation and test in Europe - Volume 1
A New Approach to the Analysis of Single Event Transients in VLSI Circuits
Journal of Electronic Testing: Theory and Applications
Journal of Electronic Testing: Theory and Applications
Early Analysis of Fault-based Attack Effects in Secure Circuits
IEEE Transactions on Computers
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Statistical fault injection: quantified error and confidence
Proceedings of the Conference on Design, Automation and Test in Europe
A novel mutation-based validation paradigm for high-level hardware descriptions
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A method to leverage pre-silicon collateral and analysis for post-silicon testing and validation
Proceedings of the 48th Design Automation Conference
Assembly-Level pre-injection analysis for improving fault injection efficiency
EDCC'05 Proceedings of the 5th European conference on Dependable Computing
Concurrent and comparative fault simulation in SystemC and its application in robustness evaluation
Microprocessors & Microsystems
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Fault-tolerant circuits are currently required in severalmajor application sectors, and a new generation of CADtools is required to automate the insertion and validationof fault-tolerant mechanisms. This paper outlines thecharacteristics of a new fault-injection platform and itsevaluation in a real industrial environment. It also detailstechniques devised and implemented within the platform tospeed-up fault-injection campaigns. Experimental resultsare provided, showing the effects of the differenttechniques, and demonstrating that they are able to reducethe total time required by fault-injection campaigns by atleast one order of magnitude.