Cost reduction and evaluation of temporary faults detecting technique
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Fault Injection Techniques and Tools
Computer
A Fault Injection Technique for VHDL Behavioral-Level Models
IEEE Design & Test
Using Run-Time Reconfiguration for Fault Injection in Hardware Prototypes
DFT '00 Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Fault List Compaction through Static Timing Analysis for Efficient Fault Injection Experiments
DFT '02 Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
EDTC '97 Proceedings of the 1997 European conference on Design and Test
MEFISTO-L: A VHDL-Based Fault Injection Tool for the Experimental Assessment of Fault Tolerance
FTCS '98 Proceedings of the The Twenty-Eighth Annual International Symposium on Fault-Tolerant Computing
New Techniques for Accelerating Fault Injection in VHDL Descriptions
IOLTW '00 Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW)
Multi-Level Fault Injection Experiments Based on VHDL Descriptions: A Case Study
IOLTW '02 Proceedings of the Proceedings of The Eighth IEEE International On-Line Testing Workshop (IOLTW'02)
New Techniques for Speeding-Up Fault-Injection Campaigns
Proceedings of the conference on Design, automation and test in Europe
A Switch-Level Algorithm for Simulation of Transients in Combinational Logic
FTCS '95 Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing
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Single event transients (SETs) on combinational gates are becoming an issue in deep sub-micron technologies, thus efficient and accurate techniques for assessing their impact are strongly required. This paper presents a new technique that embeds time-related information in the topology of the analyzed circuit, allowing evaluating the effects of SETs via zero-delay simulation instead of timed simulation. The analysis of complex designs becomes thus possible at a very limited cost in terms of CPU time. Moreover, circuits enriched with time-related information are suitable for hardware emulation thus allowing further reducing the time for SET-effect analysis, while providing the same accuracy of state-of-the-art approaches based on timed simulations. The paper reports results showing how the proposed method can be effectively used to analyze complex designs.