IEEE Transactions on Computers
Fast timing simulation of transient faults in digital circuits
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Fault behavior dictionary for simulation of device-level transients
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Efficient modeling of switch-level networks containing undetermined logic node states
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
A Switch-Level Model and Simulator for MOS Digital Systems
IEEE Transactions on Computers
Efficient analysis of single event transients
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Desing and test of systems on a chip
A New Approach to the Analysis of Single Event Transients in VLSI Circuits
Journal of Electronic Testing: Theory and Applications
Characterization of Soft Errors Caused by Single Event Upsets in CMOS Processes
IEEE Transactions on Dependable and Secure Computing
FASER: Fast Analysis of Soft Error Susceptibility for Cell-Based Designs
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
A fast, analytical estimator for the SEU-induced pulse width in combinational designs
Proceedings of the 45th annual Design Automation Conference
Efficient analytical determination of the SEU-induced pulse shape
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Switch-level soft error emulation for SET-induced pulses of variable strengths
Microelectronics Journal
FTCS'95 Proceedings of the Twenty-Fifth international conference on Fault-tolerant computing
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Abstract: A two-step switch-level algorithm for fault simulation of transients in CMOS networks is presented. The first step models the fault propagation locally from the fault injection site to the subsequent CMOS blocks. It is shown that the pulse width of a transient is a vital parameter in the propagation process. A first-order RC network model for the prediction of the width of transients is used. The second step consists of a set of rules for the propagation of fully developed transients through basic CMOS blocks. The fact that transients may fade out during propagation is efficiently modeled by taking into account their pulse widths. The proposed algorithm shows good agreement with electrical-level simulations in predicting the effects of device-level transients.