A Gate-Level Simulation Environment for Alpha-Particle-Induced Transient Faults
IEEE Transactions on Computers
Cost reduction and evaluation of temporary faults detecting technique
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Fault Injection Techniques and Tools
Computer
Fault List Compaction through Static Timing Analysis for Efficient Fault Injection Experiments
DFT '02 Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
New Techniques for Accelerating Fault Injection in VHDL Descriptions
IOLTW '00 Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW)
A Switch-Level Algorithm for Simulation of Transients in Combinational Logic
FTCS '95 Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing
Single event transients in dynamic logic
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
Study of the Effects of SEU-Induced Faults on a Pipeline Protected Microprocessor
IEEE Transactions on Computers
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The effects of charged particles striking VLSI circuits and producing single event transients (SETs) are becoming an issue for designers who exploit deep sub-micron technologies; efficient and accurate techniques for assessing their impact on VLSI designs are thus needed. This paper presents a new approach for generating the list of faults to be addressed during fault injection experiments tackling SET effects, which resorts to static timing analysis. Moreover, it proposes a simplified SET fault model, which is suitable for being adopted within a zero-delay fault simulation tool. Experimental results are reported on both standard benchmarks and real-life circuits assessing the effectiveness of the proposed techniques.