Fault Injection for Dependability Validation: A Methodology and Some Applications
IEEE Transactions on Software Engineering
FERRARI: A Flexible Software-Based Fault and Error Injection System
IEEE Transactions on Computers - Special issue on fault-tolerant computing
Experimental analysis of computer system dependability
Fault-tolerant computer system design
EXFI: a low-cost fault injection system for embedded microprocessor-based boards
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A Fault Injection Technique for VHDL Behavioral-Level Models
IEEE Design & Test
Fault Injection into VHDL Models: Experimental Validation of a Fault Tolerant Microcomputer System
EDCC-3 Proceedings of the Third European Dependable Computing Conference on Dependable Computing
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FTCS '98 Proceedings of the The Twenty-Eighth Annual International Symposium on Fault-Tolerant Computing
Time Redundancy Based Soft-Error Tolerance to Rescue Nanometer Technologies
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Algorithm-Based Fault Tolerance for Matrix Operations
IEEE Transactions on Computers
An FPGA-Based Approach for Speeding-Up Fault Injection Campaigns on Safety-Critical Circuits
Journal of Electronic Testing: Theory and Applications
FPGA-Based Fault Injection Techniques for Fast Evaluation of Fault Tolerance in VLSI Circuits
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
Multi-Level Fault Injections in VHDL Descriptions: Alternative Approaches and Experiments
Journal of Electronic Testing: Theory and Applications
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Journal of Electronic Testing: Theory and Applications
Efficient analysis of single event transients
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Desing and test of systems on a chip
A New Approach to the Analysis of Single Event Transients in VLSI Circuits
Journal of Electronic Testing: Theory and Applications
A framework for the functional verification of systemC models
International Journal of Parallel Programming
Study of the Effects of SEU-Induced Faults on a Pipeline Protected Microprocessor
IEEE Transactions on Computers
Simulated fault injections and their acceleration in SystemC
Microprocessors & Microsystems
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Simulation-based Fault Injection in VHDL descriptions is increasingly common due to the popularity of top-down design flows exploiting this language. However, the large CPU time required to perform VHDL simulations often represents a major drawback stemming from the adoption of this method. This paper presents some techniques for reducing the time to perform the Fault Injection experiments. Static and dynamic methods are proposed to analyze the list of faults to be injected, and for removing faults as soon as their behavior is known. Common features available in most VHDL simulation environments are also exploited. Experimental results show that the proposed techniques are able to reduce the time required by a typical Fault Injection campaign by a factor ranging from 51% to 96%.