Fast timing simulation of transient faults in digital circuits
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
A Gate-Level Simulation Environment for Alpha-Particle-Induced Transient Faults
IEEE Transactions on Computers
Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic
DSN '02 Proceedings of the 2002 International Conference on Dependable Systems and Networks
A Switch-Level Algorithm for Simulation of Transients in Combinational Logic
FTCS '95 Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing
A scalable soft spot analysis methodology for compound noise effects in nano-meter circuits
Proceedings of the 41st annual Design Automation Conference
Closed-Form Simulation and Robustness Models for SEU-Tolerant Design
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
A design approach for radiation-hard digital electronics
Proceedings of the 43rd annual Design Automation Conference
Efficient analytical determination of the SEU-induced pulse shape
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
On soft error rate analysis of scaled CMOS designs: a statistical perspective
Proceedings of the 2009 International Conference on Computer-Aided Design
Design as you see FIT: system-level soft error analysis of sequential circuits
Proceedings of the Conference on Design, Automation and Test in Europe
Statistical Soft Error Rate (SSER) Analysis for Scaled CMOS Designs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Single event upsets (SEUs) are becoming increasingly problematic for both combinational and sequential circuits with device scaling, lower supply voltages and higher operating frequencies. To design radiation tolerant circuits efficiently, techniques are required to analyze the effects of a particle strike on a circuit early in the design flow and also to evaluate the circuit's resilience to SEU events. In this paper, we present an analytical model for SEU induced transients in combinational circuits. The pulse width of the voltage glitch due to an SEU event is a good measure of SEU robustness and our model efficiently computes it for any combinational gate. The experimental results demonstrate that our model is very accurate with a very low pulse width estimation error of 4% compared to SPICE. Our model gains its accuracy by using a non-linear transistor current model, and by considering the effect of τβ of the radiation induced current pulse. Our analytical model is very fast and accurate, and can therefore be easily incorporated in a design flow to implement SEU tolerant circuits.