FASER: Fast Analysis of Soft Error Susceptibility for Cell-Based Designs
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Analytical modeling of SRAM dynamic stability
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
A fast, analytical estimator for the SEU-induced pulse width in combinational designs
Proceedings of the 45th annual Design Automation Conference
Guiding circuit level fault-tolerance design with statistical methods
Proceedings of the conference on Design, automation and test in Europe
Efficient analytical determination of the SEU-induced pulse shape
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
On soft error rate analysis of scaled CMOS designs: a statistical perspective
Proceedings of the 2009 International Conference on Computer-Aided Design
Statistical Soft Error Rate (SSER) Analysis for Scaled CMOS Designs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An accurate single event effect digital design flow for reliable system level design
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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A closed-form model for simulation and analysis of voltage transients caused by single-event upsets (SEUs) in logic circuits is described. A linear RC model, derived using a SPICE-based calibration of logic gates for a range of values of fanout, charge, and scale factor is presented. A full set of experimental results demonstrate that on average, the model is accurate to within 5% of the results obtained using SPICE with over 100X improvement in computational speed. Besides simulation and analysis of SEU-induced transients, the proposed model can be used to perform reliability-aware logic synthesis through the incorporation of robustness metrics to tune cell libraries.