Model for Transient Fault Susceptibility of Combinational Circuits
Journal of Electronic Testing: Theory and Applications
Closed-Form Simulation and Robustness Models for SEU-Tolerant Design
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
FASER: Fast Analysis of Soft Error Susceptibility for Cell-Based Designs
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Soft error modeling and remediation techniques in ASIC designs
Microelectronics Journal
Soft Error Rate Analysis for Combinational Logic Using an Accurate Electrical Masking Model
IEEE Transactions on Dependable and Secure Computing
Computing the Soft Error Rate of a Combinational Logic Circuit Using Parameterized Descriptors
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Similar to local variations and signal integrity problems, Single Event Effects (SEEs) are a new design concern for digital system design that arises in deep sub-micron technologies. In order to design reliable digital systems in such technologies, it is mandatory to precisely model and take into account SEEs. This paper proposes a new accurate design flow to model non-permanent SEE effects that can be applied at system level for reliable digital circuit design. Starting from low level SPICE-accurate simulations, SEEs are characterized, modeled and simulated in the digital design using commercial and well accepted standards and tools. The proposed design flow has been fully validated through a complete digital design, a cryptographic core implemented in a 32nm CMOS technology. Finally, using the SEE design flow, the paper presents some reliability impact analysis, both at standard cell level and design level.