Fast timing simulation of transient faults in digital circuits

Authors:
A. Dharchoudhury;S. M. Kang;H. Cha;J. H. Patel
Affiliations:
Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, Urbana, IL;Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, Urbana, IL;Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, Urbana, IL;Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, Urbana, IL
Venue:
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Year:
1994

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Abstract

Transient fault simulation is an important verification activity for circuits used in critical applications since such faults account for over 80% of all system failures. This paper presents a timing level transient fault simulator that bridges the gap between electrical and gate-level transient fault simulators. A generic MOS circuit primitive and analytical solutions of node differential equations are used to perform transistor level simulation with accurate MOS-FET models. The transient fault is modeled by a piecewise quadratic injected current waveform; this retains the electrical nature of the transient fault and provides SPICE-like accuracy. Detailed comparisons with SPICE3 show the accuracy of this technique and speedups of two orders of magnitude are observed for circuits containing up to 2000 transistors. Latched error distributions of the benchmark circuits are also provided.