Fast timing simulation of transient faults in digital circuits
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic
DSN '02 Proceedings of the 2002 International Conference on Dependable Systems and Networks
An Efficient BICS Design for SEUs Detection and Correction in Semiconductor Memories
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Soft-Error Rate Testing of Deep-Submicron Integrated Circuits
ETS '06 Proceedings of the Eleventh IEEE European Test Symposium
A design approach for radiation-hard digital electronics
Proceedings of the 43rd annual Design Automation Conference
A delay-efficient radiation-hard digital design approach using CWSP elements
Proceedings of the conference on Design, automation and test in Europe
Gate sizing to radiation harden combinational logic
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
| Hi-index | 0.00 |
With decreasing feature sizes, lowered supply voltages and increasing operating frequencies, the radiation tolerance of digital circuits is becoming an increasingly important problem. Many radiation hardening techniques have been presented in the literature for combinational as well as sequential logic. However, the radiation tolerance of clock generation circuitry has received scant attention to date. Recently, it has been shown that in the deep submicron regime, the clock network contributes significantly to the chip level Soft Error Rate (SER). The on-chip Phase Locked Loop (PLL) is particularly vulnerable to radiation strikes. In this paper, we present a radiation hardened PLL design. Each of the components of this design - the voltage controlled oscillator (VCO), the phase frequency detector (PFD) and the loop filter are designed in a radiation tolerant manner. Whenever possible, the circuit elements used in our PLL exploit the fact that if a gate is implemented using only PMOS (NMOS) transistors then a radiation particle strike can result only in a logic 0 to 1 (1 to 0) flip. By separating the PMOS and NMOS devices, and splitting the gate output into two signals, extreme high levels of radiation tolerance are obtained. Our PLL is tested for radiation immunity for critical charge values up to 250fC. Our results demonstrate that over a large number of radiation strikes on a number of sensitive nodes in our design, the worst case jitter is just 18%. In the worst case, our PLL returns to the locked state in 16 cycles of the VCO clock, after a radiation strike.