Fast timing simulation of transient faults in digital circuits
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
An Efficient BICS Design for SEUs Detection and Correction in Semiconductor Memories
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A fast, analytical estimator for the SEU-induced pulse width in combinational designs
Proceedings of the 45th annual Design Automation Conference
A delay-efficient radiation-hard digital design approach using CWSP elements
Proceedings of the conference on Design, automation and test in Europe
Efficient analytical determination of the SEU-induced pulse shape
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Soft Error Rate Reduction Using Circuit Optimization and Transient Filter Insertion
Journal of Electronic Testing: Theory and Applications
Proceedings of the 46th Annual Design Automation Conference
Circuit optimization techniques to mitigate the effects of soft errors in combinational logic
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Fault-tolerant synthesis using non-uniform redundancy
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
3D simulation and analysis of the radiation tolerance of voltage scaled digital circuit
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
A radiation tolerant phase locked loop design for digital electronics
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Analysis and optimization of fault-tolerant embedded systems with hardened processors
Proceedings of the Conference on Design, Automation and Test in Europe
Circuit-level design approaches for radiation-hard digital electronics
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Placement for immunity of transient faults in cell-based design of nanometer circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this paper, we present a novel circuit design approach for radiation hardened digital electronics. Our approach is based on the use of shadow gates, whose task it is to protect the primary gate in case it is struck by a heavy cosmic ion. We locally duplicate the gate to be protected, and connect a pair of transistors (or diodes) between the outputs of the original and shadow gates. These transistors turn on when the voltages of the two gates deviate during a radiation strike. Our experiments show that at the level of a single gate, our circuit structure has a delay overhead of about 4% on average, and an area overhead of over 100%. At the circuit level, however, we do not need to protect all gates. We present a methodology to selectively protect specific gates of the circuit in a manner that guarantees radiation tolerance for the entire circuit. With this methodology, we demonstrate that at the circuit level, the delay overhead is about 4% and the placed-and-routed area overhead is 30%, compared to an unprotected circuit (for delay mapped designs).