Fast timing simulation of transient faults in digital circuits
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic
DSN '02 Proceedings of the 2002 International Conference on Dependable Systems and Networks
An Efficient BICS Design for SEUs Detection and Correction in Semiconductor Memories
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Soft-Spot Analysis: Targeting Compound Noise Effects in Nanometer Circuits
IEEE Design & Test
Improving Transient Error Tolerance of Digital VLSI Circuits Using RObustness COmpiler (ROCO)
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Soft-Error Rate Testing of Deep-Submicron Integrated Circuits
ETS '06 Proceedings of the Eleventh IEEE European Test Symposium
A design approach for radiation-hard digital electronics
Proceedings of the 43rd annual Design Automation Conference
Design-for-Manufacture for Multi Gate Oxide CMOS Process
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
An Analysis Framework for Transient-Error Tolerance
VTS '07 Proceedings of the 25th IEEE VLSI Test Symmposium
IEEE Spectrum
SEU tolerant robust latch design
VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
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In this paper, we present a novel circuit design approach for radiation hardened digital electronics. Our approach is based on the use of shadow gates, whose task it is to protect the primary gate in case it is struck by a heavy cosmic ion. We locally duplicate the gate to be protected, and connect a pair of diode-connected transistors (or diodes) between the outputs of the original and shadow gates. These transistors turn on when the voltages of the two gates deviate during a radiation strike. Our experiments show that at the level of a single gate, our circuit structure has a delay overhead about 1.76% on average, and an area overhead of 277%. At the circuit level, however, we do not need to protect all gates. We present a methodology to selectively protect specific gates of the circuit in a manner that guarantees radiation tolerance for the entire circuit. With this methodology, we demonstrate that at the circuit level, the average delay overhead is about 3% and the average placed-and-routed area overhead is 28%, compared to an unprotected circuit (for delay mapped designs). We also propose an improved circuit protection algorithm to reduce the area overhead associated with our approach. With this approach for circuit protection, the area and delay overheads are further lowered.