New algorithms for gate sizing: a comparative study
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Cost reduction and evaluation of temporary faults detecting technique
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Timing driven gate duplication in technology independent phase
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
A scalable soft spot analysis methodology for compound noise effects in nano-meter circuits
Proceedings of the 41st annual Design Automation Conference
Sizing CMOS Circuits for Increased Transient Error Tolerance
IOLTS '04 Proceedings of the International On-Line Testing Symposium, 10th IEEE
Constraint-aware robustness insertion for optimal noise-tolerance enhancement in VLSI circuits
Proceedings of the 42nd annual Design Automation Conference
Load and Logic Co-Optimization for Design of Soft-Error Resistant Nanometer CMOS Circuits
IOLTS '05 Proceedings of the 11th IEEE International On-Line Testing Symposium
Soft error reduction in combinational logic using gate resizing and flipflop selection
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Computing bounds for fault tolerance using formal techniques
Proceedings of the 46th Annual Design Automation Conference
Circuit optimization techniques to mitigate the effects of soft errors in combinational logic
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Delay uncertainty reduction by gate splitting
IEEE Transactions on Circuits and Systems II: Express Briefs
RobuCheck: a robustness checker for digital circuits
Proceedings of the First Workshop on DYnamic Aspects in DEpendability Models for Fault-Tolerant Systems
Soft error modeling and remediation techniques in ASIC designs
Microelectronics Journal
Circuit-level design approaches for radiation-hard digital electronics
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Due to aggressive technology scaling, VLSI circuits are becoming increasingly susceptible to transient errors caused by single-event-upsets (SEUs). In this paper, we introduce two circuit-level techniques to efficiently yet economically improve SEU tolerance of static CMOS digital circuits. We also developed a "RObustness COmpiler (ROCO)" to integrate these techniques into the existing design flow to achieve high level of reliability at low design cost. Experiment results show that the proposed methodology is able to greatly improve the circuits' SEU tolerance with zero timing overhead and very limited area penalty.