Delay uncertainty reduction by gate splitting

Authors:
Vineet Agarwal;Jin Sun;Janet M. Wang
Affiliations:
Intel Corp., Folsom, CA;University of Arizona, Tucson, AZ;University of Arizona, Tucson, AZ
Venue:
IEEE Transactions on Circuits and Systems II: Express Briefs
Year:
2009

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Abstract

Traditional timing-variation reduction techniques are only able to decrease gate delay variation by incurring a delay overhead. In this brief, we propose a novel and effective splitting-based variation reduction technique for gates. We developed a new tool called Timing Uncertainty Reduction by Gate Splitting (TURGS), which reduces the timing variations of a circuit and presents little delay overhead at the primary output. Our experimental results show that TURGS achieves up to 20% improvement in timing variation for gates.