Load and Logic Co-Optimization for Design of Soft-Error Resistant Nanometer CMOS Circuits

Authors:
Yuvraj S. Dhillon;Abdulkadir U. Diril;Abhijit Chatterjee;Cecilia Metra
Affiliations:
Georgia Institute of Technology;Georgia Institute of Technology;Georgia Institute of Technology;University of Bologna
Venue:
IOLTS '05 Proceedings of the 11th IEEE International On-Line Testing Symposium
Year:
2005

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Abstract

Technology scaling has led to reduced noise margins and increased susceptibility of logic circuits to transient errors. In this paper, a novel methodology to increase the robustness of combinational circuits to transient errors is proposed. The number of errors propagated to the primary outputs (POs) is minimized by adding optimal amounts of capacitive loading to the POs of the logic circuit. Using a novelDelay-Assignment-Variation (DAV) based optimization methodology, the sizes, supply voltages and threshold voltages of internal gates (not primary outputs) are chosen to minimize the energy and delay overhead due to the added loads. Experiments on ISCAS'85 benchmarks show that 79.3% soft-error reduction can be obtained on the average with modest increase in circuit delay and energy. Comparison with other techniques shows that our technique has a much better energy-delay-reliability trade-off compared to others.