Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Analysis and design of low-energy flip-flops
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic
DSN '02 Proceedings of the 2002 International Conference on Dependable Systems and Networks
Time Redundancy Based Soft-Error Tolerance to Rescue Nanometer Technologies
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Characterization of Soft Errors Caused by Single Event Upsets in CMOS Processes
IEEE Transactions on Dependable and Secure Computing
Analysis and design of soft-error hardened latches
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
On Transistor Level Gate Sizing for Increased Robustness to Transient Faults
IOLTS '05 Proceedings of the 11th IEEE International On-Line Testing Symposium
Load and Logic Co-Optimization for Design of Soft-Error Resistant Nanometer CMOS Circuits
IOLTS '05 Proceedings of the 11th IEEE International On-Line Testing Symposium
A Soft Error Monitor Using Switching Current Detection
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
A Low Power Soft Error Suppression Technique for Dynamic Logic
DFT '05 Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
New Generation of Predictive Technology Model for Sub-45nm Design Exploration
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Code Design for Dependable Systems: Theory and Practical Application
Code Design for Dependable Systems: Theory and Practical Application
Soft Error Rate Reduction Using Circuit Optimization and Transient Filter Insertion
Journal of Electronic Testing: Theory and Applications
Circuit optimization techniques to mitigate the effects of soft errors in combinational logic
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Construction of SEU tolerant flip-flops allowing enhanced scan delay fault testing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-power soft error hardened latch
PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
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In VLSIs, soft errors resulting from radiation-induced transient pulses frequently occur. In recent high-density and low-power VLSIs, the operation of systems is seriously affected by not only soft errors occurring on memory systems and the latches of logic circuits but also those occurring on the combinational parts of logic circuits. The existing tolerant methods for soft errors on the combinational parts do not provide enough high tolerant capability with small performance penalty. This paper proposes a class of soft error masking circuits by using a Schmitt trigger circuit and a pass transistor. The paper also presents a construction of soft error masking latches (SEM-latches) capable of masking transient pulses occurring on combinational circuits. Moreover, simulation results show that the proposed method has higher soft error tolerant capability than the existing methods. For supply voltage V DD 驴=驴3.3 V, the proposed method is capable of masking transient pulses of magnitude 4.0 V or less.